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USB ASP Downloader for ATMega For programming the AVR microcontrollers, Atmel has provided special software that can be downloaded from the Atmel website. Software is AVRStudio. This software uses assembly language as the language of instrumentality. AVRStudio addition, there are some third party software that can be used to create programs on the AVR. These third-party software using high level programming language like C, Java, or Basic. To make removal from the computer into a chip, can be used several ways such as using JTAG cable or using artificial Atmel STK. However, you also can use the schematic circuit above to make a downloader ATMega microcontrollers based USB ports. Here is my USB downloader which I successfully created. Imade the USB ASP Downloader based ATMega8. hopefully can help you. Schematic circuit of USB ASP Downloader

atmega128 ATMEGA 128 (AVR) is a microcontroller that has been equipped for 4Kbyte in its chip EEPROM. EEPROM is separate from the AVR flash memory, and can be written, read per byte. To be able to access the EEPROM it needs to manage registers and fuse bit. To prevent errors in the writing and reading of EEPROM cultivated power supply that is used quite stable. When reading the EEPROM microcontroller stops during the four clock cycles before doing the next command, and to write EEPROM microcontroller’s clock stopped during the second cycle before doing the next command.

Minimum System ATMega 8535,16,32 Minimum system ATmega 8535/16/32 schematic circuit that is integrated with RS232 serial communication. Minimum System is a microcontroller circuit that used to work. This circuit usually consists of: 1. Crystal = to generate pulse 2. a series reset = to do the “Restart” work microcontroller Components that can be used as input and output such as: 1. display = LCD, dot matrix, seven segment, etc. 2. input = keypad, push button, etc. Schematics above are the minimum system that has been integrated with RS232 serial communication. with the RS232, then the minimum system is ready to be used to communicate between the microcontroller to the computer, or microcontroller to microcontroller.

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure. input and output port in avr atmega 8535 All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description for I/O-Ports” on page 63. Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. In addition, the Pull-up Disable – PUD bit in SFIOR disables the pull-up function for all pins in all ports when set. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions”. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. General Digital Input-output Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description for I/O-Ports” on page 63, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written a logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if no clocks are running. If PORTxn is written a logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written a logic zero when the pin is configured as an output pin, the port pin is driven low (zero). When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step.

In this section, we describe the overall architecture of the Atmel AVR ATmega16.We begin with an introduction to the concept of the reduced instruction set computer (RISC) and briefly describe the Atmel Assembly Language Instruction Set. A brief introduction is warranted because we will be programming mainly in C throughout the course of the book. We then provide a detailed description of the ATmega16 hardware architecture. Reduced Instruction Set Computer Microcontroller operation is controlled by a user-written program interacting with the fixed hardware architecture resident within the microcontroller. A specific microcontroller architecture can be categorized as accumulator-based, register-based, stack-based, or a pipeline architecture. The Atmel ATmega16 is a register-based architecture. In this type of architecture, both operands of an operation are stored in registers collocated with the central processing unit (CPU). This means that before an operation is performed, the computer loads all necessary data for the operation to its CPU. The result of the operation is also stored in a register. During program execution, the CPU interacts with the register set and minimizes slowermemory accesses.Memory accesses are typically handled as background operations. Coupled with the register-based architecture is an instruction set based on the RISC concept. A RISC processor is equipped with a complement of very simple and efficient basic operations. More complex instructions are built up from these very basic operations. This allows for efficient program operation. The Atmel ATmega16 is equipped with 131 RISC-type instructions. Most can be executed in a single clock cycle. The ATmega16 is also equipped with additional hardware to allow for the multiplication operation in two clock cycles. In many other microcontroller architectures, multiplication typically requires many more clock cycles. For additional information on the RISC architecture, the interested reader is referred to Hennessy and Patterson [3]. The Atmel ATmega16 [2] is equipped with 32 general purpose 8-bit registers that are tightly coupled to the processor’s arithmetic logic unit within the CPU. Also, the processor is designed following the HarvardArchitecture format.That is, it is equipped with separate, dedicated memories and buses for program and data information. The register-based Harvard Architecture coupled with the RISC-based instruction set allows for fast and efficient program execution and allows the processor to complete an assembly language instruction every clock cycle. Atmel indicates the ATmega16 can execute 16 million instructions per second when operating at a clock speed of 16 MHz.